SDC Consultant (Static Timing Analysis/Constraints Consultant)

iBSC

Posted on Jan 27, 2025 by iBSC
Cambridge, Cambridgeshire, United Kingdom
IT
Immediate Start
£65 - £65 Hourly
Contract/Project

My client requires a SDC Consultant (Static Timing Analysis/Constraints Consultant) that focuses on managing and validating the timing aspects of digital design in semiconductor engineering.

Required Skills:
Good knowledge of Timing Constraints:
o Proficiency in creating and validating timing constraints using Synopsys Design Constraints (SDC) format.
o Includes defining clocks, I/O constraints, timing exceptions (false paths, multicycle paths), and understanding the setup/hold timing requirements.

Ability to understand clock diagrams, clock relationships, timing exceptions, and CDC constraints:
o Expertise in analysing clock trees, clock domain crossings (CDC), and defining timing exceptions for accurate analysis.
o Knowledge of clock skew, jitter, latency, and their impact on timing closure.

Hands-on experience in developing block-level constraints:
o Ability to create and fine-tune constraints for smaller, hierarchical blocks in the design, ensuring their timing closure contributes to the overall chip design.

Scripting in Perl/TCL/Shell:
o Automation of tasks using TCL (tool control language), Perl, and Shell Scripting to generate or validate constraints, process timing reports, or streamline design workflows.


Reference: 2887707451

https://jobs.careeraddict.com/post/99078756

This Job Vacancy has Expired!

iBSC

SDC Consultant (Static Timing Analysis/Constraints Consultant)

iBSC

Posted on Jan 27, 2025 by iBSC

Cambridge, Cambridgeshire, United Kingdom
IT
Immediate Start
£65 - £65 Hourly
Contract/Project

My client requires a SDC Consultant (Static Timing Analysis/Constraints Consultant) that focuses on managing and validating the timing aspects of digital design in semiconductor engineering.

Required Skills:
Good knowledge of Timing Constraints:
o Proficiency in creating and validating timing constraints using Synopsys Design Constraints (SDC) format.
o Includes defining clocks, I/O constraints, timing exceptions (false paths, multicycle paths), and understanding the setup/hold timing requirements.

Ability to understand clock diagrams, clock relationships, timing exceptions, and CDC constraints:
o Expertise in analysing clock trees, clock domain crossings (CDC), and defining timing exceptions for accurate analysis.
o Knowledge of clock skew, jitter, latency, and their impact on timing closure.

Hands-on experience in developing block-level constraints:
o Ability to create and fine-tune constraints for smaller, hierarchical blocks in the design, ensuring their timing closure contributes to the overall chip design.

Scripting in Perl/TCL/Shell:
o Automation of tasks using TCL (tool control language), Perl, and Shell Scripting to generate or validate constraints, process timing reports, or streamline design workflows.

Reference: 2887707451

CareerAddict

Alert me to jobs like this:

Amplify your job search:

CV/résumé help

Increase interview chances with our downloads and specialist services.

CV Help

Expert career advice

Increase interview chances with our downloads and specialist services.

Visit Blog

Job compatibility

Increase interview chances with our downloads and specialist services.

Start Test

Similar Jobs

Cloud security engineer

Cambridge, Cambridgeshire, United Kingdom

Head of R&D & Chief Operating Offer

Cambridge, Cambridgeshire, United Kingdom

Bioinformatician - CRISPR - Cambridge - Outside IR35

Cambridge, Cambridgeshire, United Kingdom