SDC Consultant - Remote Working - Inside IR35 - 6+ Months Rolling Contract
Title: SDC Consultant (Static Timing Analysis/Constraints Consultant)
Location: Remote Working
Duration: 6months + Rolling
Budget: £70 - £80 per hour, all inclusive
THIS PROJECT IS INSIDE IR35
My client requires and SDC Consultant (Static Timing Analysis/Constraints Consultant) that focuses on managing and validating the timing aspects of digital design in semiconductor engineering.
Required Skills:
- Good knowledge of Timing Constraints:
- Proficiency in creating and validating timing constraints using Synopsys Design Constraints (SDC) format.
- Includes defining clocks, I/O constraints, timing exceptions (false paths, multicycle paths), and understanding the setup/hold timing requirements.
- Ability to understand clock diagrams, clock relationships, timing exceptions, and CDC constraints:
- Expertise in analysing clock trees, clock domain crossings (CDC), and defining timing exceptions for accurate analysis.
- Knowledge of clock skew, jitter, latency, and their impact on timing closure.
- Hands-on experience in developing block-level constraints:
- Ability to create and fine-tune constraints for smaller, hierarchical blocks in the design, ensuring their timing closure contributes to the overall chip design.
- Scripting in Perl/TCL/Shell:
- Automation of tasks using TCL (tool control language), Perl, and Shell Scripting to generate or validate constraints, process timing reports, or streamline design workflows.
Reference: 2884770721
SDC Consultant - Remote Working - Inside IR35 - 6+ Months Rolling Contract

Posted on Jan 21, 2025 by iBSC
Title: SDC Consultant (Static Timing Analysis/Constraints Consultant)
Location: Remote Working
Duration: 6months + Rolling
Budget: £70 - £80 per hour, all inclusive
THIS PROJECT IS INSIDE IR35
My client requires and SDC Consultant (Static Timing Analysis/Constraints Consultant) that focuses on managing and validating the timing aspects of digital design in semiconductor engineering.
Required Skills:
- Good knowledge of Timing Constraints:
- Proficiency in creating and validating timing constraints using Synopsys Design Constraints (SDC) format.
- Includes defining clocks, I/O constraints, timing exceptions (false paths, multicycle paths), and understanding the setup/hold timing requirements.
- Ability to understand clock diagrams, clock relationships, timing exceptions, and CDC constraints:
- Expertise in analysing clock trees, clock domain crossings (CDC), and defining timing exceptions for accurate analysis.
- Knowledge of clock skew, jitter, latency, and their impact on timing closure.
- Hands-on experience in developing block-level constraints:
- Ability to create and fine-tune constraints for smaller, hierarchical blocks in the design, ensuring their timing closure contributes to the overall chip design.
- Scripting in Perl/TCL/Shell:
- Automation of tasks using TCL (tool control language), Perl, and Shell Scripting to generate or validate constraints, process timing reports, or streamline design workflows.
Reference: 2884770721

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