ASIC Digital Designer

Initial 6 moth contract + extensions (long term project)

Eindhoven, Netherlands

We are looking for an experienced digital ASIC/FPGA engineer. Main activity will be RTL implementation (mainly in (System)Verilog, but VHDL is also possible) and verification (in System-Verilog) of components for a Digital Baseband for a radio system. The specification of the to-be-implemented components is usually in Matlab/Python. The following competencies are required for the candidate:

• Verilog (or VHDL) experience for RTL implementation, both for FPGA and ASIC
• System-Verilog experience for testbench development
• DSP design experience is a must (preferably for RF systems)
• Good understanding of Matlab/Python. Also able to use it for integration in the testbenches (to make it self-checking).
• Document the implemented components.