Senior VHDL/FPGA Design Engineer

Role: Senior VHDL/FPGA Design Engineer
Start date: ASAP
Contract length: 6 months
Option to extend: YES!
Salary: 500 - 600 depending on experience
Location: Leuven, Belgium

An opportunity to work for a leading company has become available at a leading company in Belgium.
Within this role you will be working with a team experienced in modern developments. You will be responsible for the VLSL design from the concept phase to testing as well as working with other VLSL designers.
The role requires speaking in Dutch and English

Desired skills:

• Expertise in VHDL, Python is an asset
• Experience with VLSI design (Xilinx (AMD)/Altera (Intel)/Actel, Microsemi, Atmel (Microchip)/Lattice/NanoXplore)
• Experience of the FPGA build process and Scripting possibilities
• Experience with automated simulation and test environment and with FPGA/ASIC design for in-space environments (ECSS-standards) are assets

If you are interested in this role please apply or reach out to Pippa Goodwin at Source Technology