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RFIC Layout Design - 40nm - 20nm - CMOS - France

CIS Electronics Engineering

Posted on Jul 28, 2021 by CIS Electronics Engineering

Not Specified, Spain
IT
Immediate Start
Annual Salary
Contract/Project


RFIC Layout Design - 40nm - 20nm - CMOS - France

For one of our existing Clients we are looking for an RFIC Layout Design Engineer working in the area of 40nm and 20nm technologies.

The key tasks will involve the following:

-Mask design of wireless communications circuits utilizing 40nm and 22nm CMOS technology.
-Collaboration with the circuit designers, and using careful RF and analog IC layout techniques for optimal design performance.
-Top level ownership and Tapeout, which includes, layout, metal fill, verification, stream out and GDS generation.

The key experience required includes:

-RFIC Layout design
-Understanding of High frequency layout techniques which optimizes the circuit performance.
-Recent RFIC project contributions on highly integrated RF transceivers,
ideally related to wireless communication systems, eg WiFi, WiMax or LTE,
on a nano-metre scale RF-CMOS technology
-Cadence Front End and Back End tools are absolutely required, including experience with auto-Routers such as VCAR

If you are available now or will be soon, please do send your CV to Richard via the application portal and we will get in touch regarding the next steps.




Reference: 1266432294

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