ASIC Verification Engineer
Posted on Apr 28, 2020 by Yoh
ASIC Verification Engineer, Lund
Are you an ASIC Verification Engineer looking for a new role?
I am working with a client in Lundwho is looking for an ASIC Verification Engineer to join their RADAR project. The main function of the role will be to plan, design and develop UVM block level test benches for products.
This is a 6 month project, but it could be written up at 3 months initially.
- Extensive experience developing and implementing Test Benches
- Expert Knowledge of SystemVerilog and UVM methodologies
- Previous experience of ASIC verification
- Top Level verification
- C or Python knowledge
If this ASIC Verification Engineer role is of interest, please apply now!