Title: DDR Subsystem/SoC Integration Senior Engineer

Location: Remote within EU (with occasional travel to France/UK)

Duration: 1 Year rolling Contract

Experience: 5-10 years

Open Positions: 3

Budget: €60 per hour

INSIDE IR35 (For candidates based in the UK only),

European candidates, this will not affect you.

Overview:
A fantastic opportunity for a skilled SoC Integration Engineer with DDR IP integration experience to work on leading-edge SoC designs.

Key Responsibilities:

• Integrate DDR IP into SoC subsystems per architecture specs

• RTL development, synthesis, timing constraint setup, and debug

• Collaborate with hardware and verification teams across Europe

Essential Skills:

• 5-10 years in ASIC/SoC integration

• Solid background in DDR controller/memory IP integration

• System Verilog, SDC, synthesis (Design Compiler/Fusion), LEC

• Strong debug experience with Verdi or equivalent