Title: PCIe Subsystem/SoC Integration Senior Engineer

Location: Remote within EU (with occasional travel to France/UK)

Duration: 1 Year rolling Contract

Experience: 5-10 years

Open Positions: 3

Budget: €60 - €65 per hour

INSIDE IR35 (For candidates based in the UK only),

European candidates, this will not affect you.

Overview:
We're looking for experienced SoC Engineers with PCIe expertise to join a leading global chip development team. You'll contribute to the integration and validation of PCIe subsystems in complex SoC designs.

Responsibilities & Requirements:

• Same as Lead PCIe role (above), but suited for mid-senior engineers (5-10 years).

• Deep hands-on experience integrating PCIe IP blocks

• Strong RTL/System Verilog and synthesis skills

• Debugging using Verdi, LEC, and gate-level flows