Title: PCIe Subsystem/SoC Integration Lead Engineer

Location: Remote within EU (with occasional travel to France/UK)

Duration: 1 Year rolling Contract

Open Positions: 1

Budget: 60 - 65 per hour

INSIDE IR35 (For candidates based in the UK only),

European candidates, this will not affect you.

Overview:
We're hiring a Senior SoC Integration Lead Engineer with deep experience in PCIe IP integration for a high-impact role within a world-class SoC team.

You'll work remotely in the EU and collaborate with global teams based in France and UK.

Responsibilities:

• Lead integration of PCIe IP blocks at subsystem and SoC levels

• Own micro-architecture and configuration of PCIe IP as per system requirements

• Write RTL in System Verilog and conduct design and code reviews

• Drive synthesis, SDC constraint management, and equivalence checking

• Collaborate with verification engineers and debug issues using Verdi

• Implement power intent using customer-specific flows

Requirements:

• 10+ years' experience in digital SoC/ASIC design and integration

• Proven experience with PCIe IP block integration

• Strong RTL coding and synthesis background

• LEC and gate-level debug experience

• Must be based in EU and available for regular syncs with France/UK teams